System controller chips, sometimes known as “North Bridge” chips, are used to interface a memory with a central processing unit (CPU) and other components, such as a graphics processing unit (GPU). The North Bridge chipset architecture is a well-known architecture to interface a CPU, memory, and other components using a dedicated North Bridge chip and corresponding South Bridge chip. Recently, however, the functionality of North Bridge chips has been expanded. For example, the function of a North Bridge chip can be included within chips providing other functions. Some references use the term “system controller” to denote a more generic application of the function conventionally provided by a North Bridge chip. Consequently, as used in this application, a system controller is a controller that provides at least the function of a North Bridge chip in regards to interfacing a CPU and a memory.
A North Bridge chip typically utilizes a bus protocol to receive read requests from a CPU. One example of a bus protocol is the front side bus (FSB) protocol used in a variety of products manufactured by the Intel Corporation. An exemplary FSB protocol is described in the book by Tom Shanley, The Unabridged Pentium 4: IA32 Processor Genealogy, MindShare, Inc. (2004), the contents of which are hereby incorporated by reference. FSB protocols typically include a sequence of transaction phases that proceed in a predefined order, such as an arbitration phase, request phase, error phase, snoop phase, response phase, and data phase.
A source-synchronous system uses a strobe or clock signal to latch or clock the address and data signals at the receiving agent. Thus, in a source-synchronous system a receiver readies itself for data transfer based on a synchronizing parameter, such as a strobe signal, provided by the signal transmitter. For example, the Pentium 4™ microprocessor, manufactured by the Intel Corporation, is designed to work with a source synchronous FSB protocol and achieve two address data transfers for each complete bus clock (BCLK). Address bus signals define an address space. In a first subphase (sometimes known as the A packet), the address of the transaction is transmitted. In a second subphase (sometimes known as the B packet), transaction type information is transmitted. Request bus signals define a currently active transaction type. An ADS# address strobe indicates the validity of a transaction on the address and request buses. An address strobe ADSTB# is sent at a half wavelength offset from the bus clock. The ADSTB# signal is used to latch the first subphase of an address and a request on a first (falling) edge of ADSTB# and latch the second subphase on a second (rising) edge. Note that a “#” symbol indicates an inversion of a signal.
In a North Bridge chip a read request is typically transferred from the clock domain of a host interface (e.g., a clock domain operating at a bus clock rate or integer multiple thereof) to the memory clock domain of a memory controller. There can be a significant time delay to transfer the read request into the memory clock domain. This is because in a conventional process all of the read request signals must be first synchronized into synchronous bus clock domains by observing the synchronous ADS# signal, and after that synchronized into the memory clock domain, which can introduce a delay of several clocks, depending upon the speed of the transfer circuit and the number of clock cycles that it takes to find a crossover point where the request signals can be transferred into the memory clock domain. This transfer delay is undesirable because it delays the data return for which the CPU is waiting before the operation is complete.
Therefore, what is desired is an improved system, apparatus, and method for a fast data request memory controller.